VSD - Static Timing Analysis - I
VLSI - Essential timing checks
Instructors:
Kunal GhoshDescription:
Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.
Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations
The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details
Hope you enjoy learning this course in the same way we enjoyed making them.
Happy Learning !!
Course content:
- Get Bonus Downloads Here.url (0.2 KB) ~Get Your Files Here !01 - Introduction and agenda
- 001 Introduction.mp4 (6.1 MB)
- 001 Introduction_en.vtt (3.7 KB)
- 002 Introduction to timing path and arrival time.mp4 (21.5 MB)
- 002 Introduction to timing path and arrival time_en.vtt (11.2 KB)
- 003 Introduction to required time and slack.mp4 (24.6 MB)
- 003 Introduction to required time and slack_en.vtt (10.6 KB)
- 004 Introduction to basic categories of setup and hold analysis.mp4 (22.6 MB)
- 004 Introduction to basic categories of setup and hold analysis_en.vtt (11.4 KB)
- 005 Introduction to data check and latch timing.mp4 (29.5 MB)
- 005 Introduction to data check and latch timing_en.vtt (10.8 KB)
- 006 Introduction to slew, load and clock checks.mp4 (36.9 MB)
- 006 Introduction to slew, load and clock checks_en.vtt (9.8 KB)
- 001 Convert logic gates into nodes.mp4 (23.6 MB)
- 001 Convert logic gates into nodes_en.vtt (11.9 KB)
- 002 Compute actual arrival time (AAT).mp4 (27.2 MB)
- 002 Compute actual arrival time (AAT)_en.vtt (11.8 KB)
- 003 Compute required arrival time (RAT).mp4 (25.8 MB)
- 003 Compute required arrival time (RAT)_en.vtt (10.0 KB)
- 004 Compute slack and introduction to GBA-PBA analysis.mp4 (31.9 MB)
- 004 Compute slack and introduction to GBA-PBA analysis_en.vtt (11.8 KB)
- 005 Convert pins to nodes and compute AAT, RAT and slack.mp4 (34.5 MB)
- 005 Convert pins to nodes and compute AAT, RAT and slack_en.vtt (12.7 KB)
- 001 Introduction to transistor level circuit for flops.mp4 (21.0 MB)
- 001 Introduction to transistor level circuit for flops_en.vtt (10.3 KB)
- 002 Negative and positive latch transistor level operation.mp4 (20.7 MB)
- 002 Negative and positive latch transistor level operation_en.vtt (10.1 KB)
- 003 Library setup time calculation.mp4 (30.6 MB)
- 003 Library setup time calculation_en.vtt (10.5 KB)
- 004 Clk-q delay calculation.mp4 (38.1 MB)
- 004 Clk-q delay calculation_en.vtt (12.1 KB)
- 005 Steps to create eye diagram for jitter analysis.mp4 (21.9 MB)
- 005 Steps to create eye diagram for jitter analysis_en.vtt (10.5 KB)
- 006 Jitter extraction and accounting in setup timing analysis.mp4 (32.1 MB)
- 006 Jitter extraction and accounting in setup timing analysis_en.vtt (10.2 KB)
- 001 Setup analysis - graphical to textual representation.mp4 (14.5 MB)
- 001 Setup analysis - graphical to textual representation_en.vtt (10.0 KB)
- 002 Hold analysis with real clocks.mp4 (10.7 MB)
- 002 Hold analysis with real clocks_en.vtt (12.6 KB)
- 003 Hold analysis - graphical to textual representation.mp4 (8.4 MB)
- 003 Hold analysis - graphical to textual representation_en.vtt (9.4 KB)
- 001 Sources of variation - etching.mp4 (13.5 MB)
- 001 Sources of variation - etching_en.vtt (13.6 KB)
- 002 Sources of variation - oxide thickness.mp4 (10.2 MB)
- 002 Sources of variation - oxide thickness_en.vtt (11.1 KB)
- 003 Relationship between resistance, drain current and delay.mp4 (14.1 MB)
- 003 Relationship between resistance, drain current and delay_en.vtt (14.1 KB)
- 001 OCV based setup timing analysis.mp4 (14.3 MB)
- 001 OCV based setup timing analysis_en.vtt (12.6 KB)
- 002 Setup timing analysis after pessimism removal.mp4 (13.3 MB)
- 002 Setup timing analysis after pessimism removal_en.vtt (11.7 KB)
- 003 OCV based hold timing analysis.mp4 (8.4 MB)
- 003 OCV based hold timing analysis_en.vtt (7.3 KB)
- 004 Hold timing analysis after pessimism removal.mp4 (14.1 MB)
- 004 Hold timing analysis after pessimism removal_en.vtt (11.9 KB)
- 001 Conclusion and next topics!!.mp4 (2.5 MB)
- 001 Conclusion and next topics!!_en.vtt (3.2 KB)
- Bonus Resources.txt (0.4 KB)
Download this course:
file type : Torrent
Files :
- Torrent 1572.7 MB
Top reviews:
Show reviews
Yes, the course is a good start for someone looking for a fresh start in STA analysis.
very crisp and clearly explained with good graphs and visuals
Amazing course for basic STA understanding
I come from an Electrical Engineering background, and I am currently in the semiconductor industry. These videos on Physical Design Flow, TCL, Static Timing Analysis by Kunal Sir has made me dive deeper into this domain. The video lectures not only provide a basic structure and understanding, but encourage in learning more. I am glad to have taken this course and have been fortunate in developing my VLSI based profile.
Good
This is a good course for beginners who are just getting into VLSI design flow.
Basic concepts explained pretty well with great analogies
Transcript base on subtitle , but subtitle is not right
The explanation of the timing analysis concepts are very clear and nicely represented through timing diagrams.
explained everything in a very good way.
The course is very well designed considering the beginners and provides understanding of setup and hold time analysis which is a must to start with for a fresher in VLSI domain.
Covered the basics clearly. Fully satisfied.